In computer systems, a central processing unit (CPU) may access memory by providing an address that indicates a unique location of a group of memory cells that collectively store a data element. The CPU may initiate a bus cycle by providing the address to an address bus, and one or more control signals to signal that the address is valid and the bus cycle has begun. A read/write control signal then indicates whether the access is to be a read access or a write access. Subsequently, the data element may either be read from a data bus if the bus cycle is a read cycle, or provided to the data bus if the bus cycle is a write cycle.
A number of operations may be taken when performing an initial access to memory. These operations may make the initial access relatively slow. As described above, certain signals may be set to begin the process. Next, the address may be sent to the memory. After these steps, the data itself may be transferred. Because of this operational overhead, or latency, the initial access to memory may take a relatively long time, e.g., four to seven clock cycles in many devices.
To reduce the latency of the memory, some memory devices read a block four 64-bit words (256 bits or 32 bytes) from memory consecutively for each access. An advantage of this “burst access mode,” or “bursting,” is avoiding repetition of the overhead of the initial access for the subsequent three accesses. The subsequent accesses may be shortened to one to three clock cycles instead of four to seven clock cycles.
A memory device that supports bursting may not be byte-addressable. Instead of accessing a memory location at a specific byte address, the memory device may retrieve a multi-byte block of data elements. Some of the data elements in the block of data may not be valid for the request. Accordingly, it may be advantageous to provide a method for determining the valid data elements in a burst-accessed word.